#yosys -TQd -v 1 -L map.log -c map.tcl


proc read_proj { fp }  {

	set cfg [dict create other_title  "hello" ]
	set sect "other"
	
	while {[gets $fp tline] != -1 } {
	
		set tline [string trim $tline ]
		if { [string length $tline ] <= 3 }  {
			continue
		}
		
		if { [string match {\[*\]} $tline] }  {
		
			set tline [string range $tline 1 end-1]
			
			if { $tline == "GuiMigrateSetupPage" }  {
				set sect "setup"
			} elseif { $tline == "GuiMigrateRunPage"} {
				set sect "run"
			} elseif { $tline == "GuiMigrateQuartusPage" }  {
				set sect "quartus"
			} else {
				set sect "other"
			}
			
			continue
		}
		
		set tidx [string first "=" $tline ]
		
		if { ($tidx <= 0) || (($tidx+1) >= [string length $tline]) }  {
			continue
		}
		
		set tkey [string range $tline 0 $tidx-1 ]
		set tval [string range $tline $tidx+1 end ]
		
		dict append cfg "${sect}_${tkey}" $tval
	}
	
	
	return $cfg
}


set prjs [glob -type f -nocomplain  *.proj]
if { [llength $prjs] == 0 }  {
	error "not found proj file in curr directory"
}

set pjnm [lindex $prjs 0]
set pjfp [open $pjnm r]
set pjcfg [read_proj $pjfp ]
close $pjfp

################################################################################################################################
# 工程中的原始 af_map.tcl 需要如下 3 个变量:
#   verilogs :   list : 表示 yosys 综合过程设计的 源代码文件.
#     DESIGN : string : 表示用户自定义个的 项目名字.
# TOP_MODULE : string : 表示 top module 的名字, 通常跟 design 相同.
################################################################################################################################

if { [dict exists $pjcfg setup_design ] }  {
	set DESIGN [dict get $pjcfg setup_design ]
	set TOP_MODULE [dict get $pjcfg setup_design ]
} else {
	error "not found setup_design in proj file."
}

if { [dict exists $pjcfg quartus_verilogFiles ] }  {
	
	set verilogs {}
	foreach tmp [split [dict get $pjcfg quartus_verilogFiles] "," ] {
		lappend verilogs [string trim $tmp ]
	}
	
	if { [llength $verilogs] <= 0 }  {
		error "verilog files not define in proj file"
	}

} else {
	error "not found quartus_verilogFiles in proj file."
}

puts $verilogs
puts "DESIGN: $DESIGN"

################################################################################################################################

yosys -import


if { ! [info exists RETIMING] } {
  set RETIMING "100"
}
if { $RETIMING == "true" } {
  set RETIMING "100"
} elseif { $RETIMING == "false" } {
  set RETIMING "None"
}
if { ! [info exists IOPAD] } {
  set IOPAD true
}

foreach verilog $verilogs {
  read_verilog -sv -overwrite -noautowire -DALTA_SYN "$verilog"
}

#family:
    read_verilog -DALTA_LIB -sv -lib +/agm/rodina/cells_sim.v
    read_verilog -DALTA_SYN -sv +/agm/common/m9k_bb.v
    read_verilog -DALTA_SYN -sv +/agm/common/altpll_bb.v
    read_verilog -DALTA_LIB -sv -lib +/agm/rodina/alta_sim.v
    read_verilog -DALTA_SYN -sv +/agm/rodina/alta_sim.v
    read_verilog -DALTA_SYN -sv +/agm/common/alta_bb.v
    hierarchy -check -top $TOP_MODULE -libdir .

#flatten:
   #yosys proc
    flatten
    tribuf -logic
    deminout

    set alta_ips {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp}
    select -none
    foreach alta_ip $alta_ips {
      select -add */t:$alta_ip
    }
    select -set keep_cells %
    select -clear
    setattr -set keep 1 @keep_cells

#coarse:
    synth -run coarse -top $TOP_MODULE
    for {set nn 0} {$nn < 10} {incr nn} {
      proc_dff
    }

#map_bram:
    memory_libmap -lib +/agm/common/brams_m9k.txt
    techmap -autoproc -map +/agm/common/brams_map_m9k.v
    yosys proc
    read_verilog -DALTA_SYN -sv +/agm/rodina/alta_sim.v
    hierarchy -check -top $TOP_MODULE
    flatten

#map_ffram:
    opt -fast -mux_undef -undriven -fine -full
    memory_map
    opt -undriven -fine
    techmap -autoproc -map +/techmap.v
    techmap -autoproc -map +/agm/rodina/arith_map.v
    yosys proc
    opt -full
    yosys rename -wire -suffix _reg t:$*DFF*
    clean -purge
    setundef -undriven -zero
    if { $RETIMING != "None" } {
      abc -markgroups -dff -D $RETIMING
    }

#map_ffs:
    dfflegalize -cell \$_DFFE_????_ 0 -cell \$_SDFFCE_????_ 0 -cell \$_DLATCH_?_ x -cell \$_ALDFFE_???_ 0
    techmap -autoproc -map +/agm/common/ff_map.v
    yosys proc
    opt -full
    clean -purge
    setundef -undriven -zero
    abc -markgroups -dff -D 1
    agm_dffeas

##opts:
    opt_expr -mux_undef -undriven -full
    opt_merge
    opt_clean
    autoname
 
#map_luts:
    abc -lut 4
    clean

#map_cells:
    if { $IOPAD } {
      iopadmap -bits -outpad \$__outpad I:O -inpad \$__inpad O:I -toutpad \$__toutpad E:I:O -tinoutpad \$__tinoutpad E:O:I:IO
    }
    techmap -autoproc -map +/agm/rodina/cells_map.v
    clean -purge
    autoname

#check:
    hierarchy -check
    stat
    check -noinit
    blackbox =A:whitebox

#vqm:
    write_verilog -simple-lhs -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm

